1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to transistors comprising a high-k metal gate electrode structure formed in an early manufacturing stage.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistors, which represent the dominant circuit elements in complex integrated circuits. For example, several hundred million transistors may be provided in presently available complex integrated circuits, wherein performance of the transistors in the speed critical signal paths substantially determines overall performance of the integrated circuit. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies, such as CPUs, storage chips and the like. During the fabrication of complex integrated circuits using CMOS technology, the complementary transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface positioned between highly doped drain and source regions and an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
When reducing the channel length of field effect transistors, generally an increased degree of capacitive coupling is required in order to maintain controllability of the channel region, which may typically require an adaptation of a thickness and/or material composition of the gate dielectric material. For example, for a gate length of approximately 80 nm, a gate dielectric material based on silicon dioxide with a thickness of less than 2 nm may be required in high-speed transistor elements, which may, however, result in increased leakage currents caused by hot carrier injection and direct tunneling of charge carriers through the extremely thin gate dielectric material. Since a further reduction in thickness of silicon dioxide-based gate dielectric materials may increasingly become incompatible with thermal power requirements of sophisticated integrated circuits, in some approaches, the inferior controllability of the channel region of the short channel transistors caused by the continuous reduction of the critical dimensions of gate electrode structures has been addressed by an appropriate adaptation of the material composition of the gate dielectric material.
To this end, it has been proposed that, for a physically appropriate thickness of a gate dielectric material, i.e., for a thickness resulting in an acceptable level of gate leakage currents, a desired high capacitive coupling may be achieved by using appropriate material systems, which have a significantly higher dielectric constant compared to the conventionally used silicon dioxide-based materials. For example, dielectric materials including hafnium, zirconium, aluminum and the like may have a significantly higher dielectric constant and are therefore referred to as high-k dielectric materials, which are to be understood as materials having a dielectric constant of 10.0 or higher when measured in accordance with typical measurement techniques. As is well known, the electronic characteristics of the transistors also strongly depend on the work function of the gate electrode material, which in turn influences the band structure of the semiconductor material in the channel regions separated from the gate electrode material by the gate dielectric layer. In well-established polysilicon/silicon dioxide-based gate electrode structures, the corresponding threshold voltage, that is strongly influenced by the gate dielectric material and the adjacent electrode material, is adjusted by appropriately doping the polysilicon material in order to appropriately adjust the work function of the polysilicon material at the interface between the gate dielectric material and the electrode material. Similarly, in gate electrode structures including a high-k gate dielectric material, the work function has to be appropriately adjusted for N-channel transistors and P-channel transistors, respectively, which may require appropriately selected work function adjusting metal species, such as lanthanum for N-channel transistors and aluminum for P-channel transistors and the like. For this reason, corresponding metal-containing conductive materials may be positioned close to the high-k gate dielectric material in order to form an appropriately designed interface that results in the target work function of the gate electrode structure. In some conventional approaches, the work function adjustment is performed at a very late manufacturing stage, i.e., after any high temperature processes, after which a placeholder material of the gate electrode structures, such as polysilicon, is replaced by an appropriate work function adjusting species in combination with an electrode metal, such as aluminum and the like. In this case, however, very complex patterning and deposition process sequences are required in the context of gate electrode structures having critical dimensions of 50 nm and significantly less, which may result in severe variations of the resulting transistor characteristics.
Therefore, other process strategies have been proposed in which the work function adjusting materials may be applied in an early manufacturing stage, i.e., upon forming the gate electrode structures, wherein the metal species may be thermally stabilized and encapsulated in order to obtain the desired work function and thus threshold voltage of the transistors without being unduly influenced by the further processing. It turns out that, for many appropriate metal species and metal-containing electrode materials, an appropriate adaptation of the band gap of the channel semiconductor material may be required, for instance, in the P-channel transistors, in order to appropriately set the work function thereof. For this reason, frequently a so-called threshold adjusting semiconductor material, for instance in the form of a silicon/germanium mixture, is formed on the active regions of the P-channel transistors prior to forming the gate electrode structures, thereby obtaining the desired offset in the band gap of the channel semiconductor material.
With reference to FIGS. 1a-1d, a conventional process will be described in more detail, when complementary transistors are formed so as to provide a high-k metal gate electrode structure in an early phase of the process.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in which a silicon/germanium material is to be provided in the channel area of one type of transistor on the basis of an epitaxial growth process, while the threshold voltage of the other transistor type is adjusted by appropriately selecting the material system in the associated gate electrode structure. In the manufacturing stage shown, the device 100 comprises a substrate 101 and a silicon-based semiconductor layer 102, wherein the substrate 101 and the semiconductor layer 102 form a bulk configuration or a silicon-on-insulator (SOI) configuration, depending on the desired transistor architecture. For example, for an SOI configuration, a buried insulating layer (not shown) is formed below the semiconductor layer 102 and thus isolates the layer 102 with respect to the substrate 101. The semiconductor layer 102 further comprises isolation structures 102C, such as shallow trench isolations, which laterally delineate semiconductor regions or active regions, two of which, indicated as 102A, 102B, are illustrated in FIG. 1a. In the example shown, the active region 102A corresponds to the semiconductor region of a P-channel transistor, while the active region 102B corresponds to an N-channel transistor. An appropriate mask layer 103, such as a silicon dioxide material, may be formed on the active region 102B in order to act as a deposition mask for the selective epitaxial growth of a silicon/germanium material in the active region 102A. In some illustrative approaches, typically a recess 102R is provided in the region 102A prior to actually depositing the silicon/germanium material.
The semiconductor device 100 as illustrated in FIG. 1a may be formed on the basis of the following processes. The isolation structure 102C may be formed by using sophisticated lithography, etch, deposition and planarization techniques, wherein, prior to or after forming the isolation structure 102C, appropriate well dopant species may be incorporated into the active regions 102A, 102B in order to define the basic transistor characteristics. To this end, any well-established implantation techniques and masking regimes may be applied. Thereafter, the mask 103 is formed, for instance, by oxidation, deposition and the like, wherein a non-desired portion of the mask material is removed from above the active region 102A, for instance by applying a resist mask and performing any appropriate etch process. Furthermore, as illustrated, the recess 102R may be formed with an appropriate depth so as to obtain a desired surface topography after the deposition of the silicon/germanium material. Next, a selective epitaxial growth process is performed after any cleaning processes and the like in which process parameters are established in such a manner that a significant semiconductor material deposition is substantially restricted to exposed surface areas of the active region 102A, while any pronounced deposition on dielectric surface areas, such as the mask 103 and the isolation structure 102C is suppressed. To this end, well-established chemical vapor deposition (CVD) techniques with process temperatures in the range of 650-750° C. have been developed on the basis of appropriately selected gas flow rates and process pressure, wherein the fraction of germanium in the silicon/germanium mixture may be set on the basis of controlling the corresponding gas flow rates. As previously explained, the resulting electronic characteristics, in particular the resulting threshold voltage, may significantly depend on the thickness of the silicon/germanium material and the material composition thereof, i.e., the germanium fraction contained therein. For example, a thickness of approximately 8-12 nm and a germanium content of up to 25 percent may be used in order to obtain the required threshold voltage.
FIG. 1b schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As illustrated, a silicon/germanium mixture or alloy 104 is formed in the active region 102A and thus represents a portion thereof, thereby providing the desired band gap offset, as discussed above. Furthermore, a gate electrode structure 160A of a P-channel transistor 150A is formed on the channel material 104 and may comprise a gate dielectric material 163A and a metal-containing electrode material 162A, followed by a further electrode material 161, such as silicon and the like. Furthermore, the materials 163A, 162A, 161 may be encapsulated by a spacer structure 165, for instance provided in the form of a silicon nitride material and the like, while also a cap layer 164 may be provided, for instance in the form of silicon dioxide, silicon nitride and the like. Similarly, a gate electrode structure 160B of an N-channel transistor 150B may be formed on the active region 102B and may have basically a similar configuration as the gate electrode structure 160A. That is, a gate dielectric material 163B in combination with a metal-containing electrode material 162B and the electrode material 161 may be provided in combination with the spacer structure 165 and a cap layer 164. It should be appreciated that the gate dielectric materials 163A, 163B may have basically the same configuration and may, however, differ in a work function adjusting species that may have been incorporated therein during the previous processing. For example, frequently, appropriate species may be diffused into the gate dielectric material in order to appropriately modify the characteristics thereof in view of achieving a desired overall work function and thus threshold voltage. Moreover, as discussed above, the gate dielectric layers 163A, 163B comprise a high-k dielectric material such as hafnium oxide and the like, possibly in combination with a thin conventional dielectric material, for instance in the form of silicon oxynitride and the like in view of superior interface characteristics. The metal-containing electrode materials 162A, 162B may have substantially the same composition or may differ with respect to a work function adjusting species, depending on the overall process strategy applied for forming the gate electrode structures 160A, 160B.
A typical process flow for forming the semiconductor device 100 as illustrated in FIG. 1b may comprise the following processes. First, the basic material composition of the gate dielectric layers 163A, 163B may be provided, possibly in combination with any work function adjusting metal species and additional cap materials, such as titanium nitride and the like, and any appropriate treatment, such as anneal processes and the like, may be applied in order to adjust the overall characteristics of the gate dielectric materials 163A, 163B. Thereafter, the same or different materials may be deposited for the layers 162A, 162B followed by the deposition of the material 161, for instance in the form of amorphous or polycrystalline silicon. Moreover, any further material, such as the cap material 164, is provided and the resulting layer stack is patterned on the basis of sophisticated lithography and etch techniques. Thereafter, the spacer structure 165 is formed by any appropriate deposition and etch strategy in order to confine, in particular, the sensitive materials 163A, 163B and 162A, 162B.
Consequently, by means of the channel material 104, an appropriate threshold voltage for the transistor 150A could be in principle obtained, wherein, however, significant defects have been observed in the material 104, as indicated by 104A, when the material 104 is provided with a thickness and material composition, as specified above. However, corresponding defects in the channel region of the transistor 150A may result in significant variation of transistor characteristics or may even result in a non-acceptable transistor performance.
FIG. 1c schematically illustrates the semiconductor device 100 in a further advanced manufacturing stage. As shown, the transistor 150A comprises the gate electrode structure 160A, possibly with an additional spacer structure 166, which may include the spacer structure 165 (FIG. 1b). The spacer structure 166 may be used for defining the lateral and vertical dopant profile of drain and source regions 152. Similarly, the transistor 150B comprises the gate electrode structure 160B and corresponding drain and source regions 152, which, however, have an inverse conductivity type compared to the regions 152 of the transistor 150A. The transistors 150A, 150B may be formed on the basis of any appropriate process strategy for providing the spacer structure 166 and the drain and source regions 152.
In sophisticated applications, the final dopant profile in the drain and source regions is substantially defined by the previously performed implantation processes, while any further dopant diffusion upon activating the implanted drain and source dopant species is considered inappropriate, at least in some manufacturing stages of providing the drain and source dopant species. To this end, frequently advanced anneal techniques may be applied, such as flashlight-based anneal processes, in which pulses of light of different wavelengths may be generated in order to deposit a sufficiently high energy in and at the surface of the semiconductor device so as to create required temperatures that allow an efficient activation of the dopants. That is, during the corresponding advanced flashlight-based anneal techniques, high temperatures are generated in a thin surface layer without unduly heating the remaining portion of the substrate. Since the corresponding heat may be generated within short time intervals, an efficient activation of the dopant species, i.e., a positioning of the dopant atoms at lattice sites, may be accomplished without causing undue dopant diffusion, which may typically require longer time intervals. In other cases, laser-based anneal techniques may be applied in which laser pulses of a specific wavelength may be scanned across the device in order to appropriately control the surface temperature and thus the activation conditions of the dopant species. Also in this case, a very efficient activation of dopants may be accomplished, while at the same time the diffusion activity may be adjusted to a very low level. It should be appreciated that, in particular, laser-based anneal techniques may also be combined with conventional anneal processes, which may be performed on the basis of moderately low temperatures so as to initiate superior re-crystallization, also without generating significant dopant diffusion. Consequently, laser-based anneal processes are frequently considered as a preferred anneal technique to be applied in sophisticated semiconductor devices. It turns out, however, that in particular the laser-based anneal process may result in significant variations of the threshold voltage of transistors and in particular of the N-channel transistor 150B. Without intending to restrict the present application to any theory, it is nevertheless believed that, during the laser-based anneal process, a significant modification of the characteristics of the high-k metal gate electrode structure may be induced, in particular in N-channel transistors such as the transistor 150B.
FIG. 1d schematically illustrates a top view of the semiconductor device 100 during a laser-based anneal process 110. As explained above, during the laser anneal process 110, the temperature of a corresponding portion of the device 100 may be locally increased within a thickness of several micrometers, thereby facilitating the migration of dopant species to a next lattice site. During the time interval of elevated temperature acting on the transistors 150A, 150B, and in particular on the gate electrode structures 160A, 160B, it is assumed that a modification may take place in the sensitive materials 163B, 163A, 162B, 162A (FIG. 1c). For example, it is assumed that high-k dielectric materials may have an increased affinity to oxygen, while also a certain degree of oxygen migration may occur during high temperature processes, which may result in a certain degree of oxygen vacancies, according to some non-confirmed theories. During the process 110, oxygen may be incorporated into the gate electrode structures 160A, 160B, preferably from the edges of the active regions 102A, 102B, for instance due to the presence of the isolation region 102C, at areas in which the gate electrode structures 160A, 160B are in contact with the isolation region 102C. Consequently, it is believed that an increased oxygen ingress into the gate electrode structures 160A, 160B may be induced, as indicated by 111, due to the laser-based anneal process 110. Although the reason is still unknown, a corresponding modification may occur in N-channel transistors to a significantly higher degree compared to P-channel transistors. Thus, the characteristics of the gate electrode structure 160B may be locally modified in the transistor 150B and may thus result, for instance, in a significant shift of the threshold voltage locally at corresponding edges of the active region 102B, which may thus also result in a shift of threshold voltage for the entire transistor 150B. Since the corresponding modification of the high-k dielectric material and/or of the corresponding conductive cap material may be locally restricted to the corresponding edge regions, the overall influence on the transistor 150B may be higher for a reduced transistor width, as indicated by 150W, while the corresponding variation in threshold voltage may be less pronounced upon increasing the transistor width 150W. As a consequence, since typically a plurality of different transistor widths may have to be implemented in complex semiconductor devices, a pronounced variation of the threshold voltages may be observed, in particular for N-channel transistors, thereby making the approach of providing the high-k metal gate electrode structures in an early manufacturing stage less attractive in complex semiconductor devices.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.